The present invention relates to a character multiplexed television transmission system which transmits character information by multiplexing the character signal in a vertical retrace blanking period, in particular, the present invention relates to such a system which transmits coded digital character information with a digital error correction facility.
An error correction system for a character multiplex television transmission (teletext) system which uses coded digital signal has been known in the Japanese patent application Nos. 6579/83, 54002/83, and 90017/83, (Japanese laid open publication Nos. 133751/84, 181841/84 and 216388/84, respectively), which use a packet with 272 bits having 190 data bits and 82 parity bits.
FIG. 1 shows a brief block diagram of such a prior system, in which the numeral 1 is a bus coupled to a CPU (central processing unit), and said bus line 1 is coupled to the output port 2 and the input port 3. The output port 2 supplies the uncorrected data 5 to the error correction circuit 4, which includes a parallel-serial converter, a serial-parallel converter, a syndrome register, a data register, and a majority circuit to correct errors of said (272, 190) codes. The error correction circuit 4 supplies the corrected data 6 and the ready signal 10 to the input port 3. The error correction circuit 4 receives from the CPU, the start signal 7, the load signal 8, the correct signal 9 through the output port 2.
In FIG. 1, the CPU supplies the start signal 7 to the error correction circuit 4, before the error correction operation, so that the syndrome register in the circuit 4 is initiated. Then, the predetermined number of bits (8 bits, or 16 bits) of uncorrected data is supplied to the error correction circuit 4 by the CPU through the bus line 1 and the output port. The load signal 8 is also supplied to the error correction circuit 4 by the CPU for every supply of 8 bits or 16 bits of uncorrected data to the error correction circuit 4. The error correction circuit 4 converts first the input data (8 bits or 16 bits) which is in parallel form to a serial form, then, the serial data is stored in the data register and the syndrome register (not shown). Therefore, 34 times of transfer operation is requested to transfer a single packet which has 272 bits when an 8 bits CPU is used (when 16 bits CPU is used, 17 times of transfer operation is requested). When 272 bits of data is transferred into the syndrome register in the error correction circuit 4, a syndrome is obtained. Then, the CPU supplies the correct signal to the error correction circuit 4 through the bus line 1 and the output port 2, and the error correction circuit 4 corrects an error or errors of data, then, the corrected data (8 bits or 16 bits) returns to the CPU through the serial-parallel conversion, the input port 3, and the bus line 1. When 34 times of return operation finishes (8 bits CPU), the correction of 272 bits finishes.
The ready signal 10 informs the CPU if the CPU may load the uncorrected 8 bits data (or 16 bit data) to the error correction circuit, or the CPU may read the corrected 8 bits data (or 16 bits data).
The structure of FIG. 1 has the advantage that the circuit structure is simple and the error correction of (272, 190) code is performed in memory mapped I/O format, however, it has the disadvantage that the CPU must write and/or read data in the error correction circuit 4, so the load on the CPU is heavy.
It should be noted that up to 12 packets are mounted in each vertical blanking period in the Japanese character transmission television (teletext) system. Therefore, the time requested for error correction is; EQU 34 bytes.times.2.times.12 packets=816 bytestime
where 1 byte has 8 bits. Further, the time for providing a load instruction, providing a correct instruction, testing a ready signal is requested, and this all adds to the load on the CPU. That heavy work of a CPU can disturb other jobs of a CPU, including decoding characters, and/or displaying characters.